DS003-1 Datasheet, PDF (17/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
Table 8: Master/Slave Serial Mode Programming Switching
Description
Figure
References
DIN setup/hold, slave mode
1/2
DIN setup/hold, master mode
1/2
DOUT
3
High time
4
CCLK
Low time
5
Maximum Frequency
Frequency Tolerance, master mode with
respect to nominal
Symbol
T_DCC/T_CCD
T_DSCK/T_CKDS
T_CCO
T_CCH
T_CCL
F_CC
Values
5.0 / 0
5.0 / 0
12.0
5.0
5.0
66
+45%
–30%
Units
ns, min
ns, min
ns, max
ns, min
ns, min
MHz, max
3.3V
VCC
Optional Pull-up
Resistor on Done¹
M0 M1
M2
DOUT
VIRTEX
MASTER
SERIAL
CCLK
DIN
PROGRAM
DONE
INIT
4.7 K
XC1701L
CLK
DATA
CE
RESET/OE
CEO
(Low Reset Option Used)
M0 M1
M2
DIN
DOUT
CCLK
VIRTEX,
XC4000XL,
SLAVE
PROGRAM
DONE
INIT
PROGRAM
Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to the common DONE line.
Figure 12: Master/Slave Serial Mode Circuit Diagram
xcv_12_091499
DIN
CCLK
DOUT
(Output)
1 T_DCC
2 T_CCD
4 T_CCH
3 T_CCO
5 T_CCL
Figure 13: Slave-Serial Mode Programming Switching Characteristics
X5379_a
DS003-2 (v2.8.1) December 9, 2002
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
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