DS003-1 Datasheet, PDF (36/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
I/O Standard Global Clock Input Adjustments
Description
Data Input Delay Adjustments
Standard-specific global clock input
delay adjustments
Symbol
Standard⁽¹⁾
Min
T_GPLVTTL
LVTTL
0
T_GPLVCMOS
2
T_{GPPCI33_3}
T_{GPPCI33_5}
T_{GPPCI66_3}
T_GPGTL
LVCMOS2
PCI, 33 MHz, 3.3
V
PCI, 33 MHz, 5.0
V
PCI, 66 MHz, 3.3
V
GTL
–0.02
–0.05
0.13
–0.05
0.7
T_GPGTLP
GTL+
0.7
T_GPHSTL
HSTL
0.7
T_GPSSTL2
SSTL2
0.6
T_GPSSTL3
SSTL3
0.6
T_GPCTT
CTT
0.7
T_GPAGP
AGP
0.6
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Speed Grade
-6
-5
0
0
–0.04 –0.04
–0.11 –0.12
0.25 0.28
–0.11 –0.12
0.8
0.9
0.8
0.8
0.7
0.7
0.52 0.51
0.6 0.55
0.7
0.7
0.54 0.53
-4
0
–0.05
–0.14
0.33
–0.14
0.9
0.8
0.7
0.50
0.54
0.7
0.52
Units
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
ns,
max
Module 3 of 4
12
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DS003-3 (v3.2) September 10, 2002
Production Product Specification