DS003-1 Datasheet, PDF (43/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Speed Grade
Description
Symbol
Device
Min
-6
-5
-4
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
No Delay
T_PSDLL/T_PHDLL
Global Clock and IFF, with DLL
XCV50
0.40 / –0.4 1.7 /–0.4 1.8 /–0.4 2.1 /–0.4 ns,
min
XCV100 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV150 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV200 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV300 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV400 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV600 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV800 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
IFF = Input Flip-Flop or Latch
XCV1000 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. DLL output jitter is already included in the timing calculation.
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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