DS003-1 Datasheet, PDF(8/76 Page) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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DS003-1 Datasheet, PDF (8/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtexâ¢ 2.5 V Field Programmable Gate Arrays

more I/O pins convert to VREF pins. Since these are always

a superset of the VREF pins used for smaller devices, it is

possible to design a PCB that permits migration to a larger

device if necessary. All the VREF pins for the largest device

anticipated must be connected to the VREF voltage, and not

used for I/O.

In smaller devices, some VCCO pins used in larger devices

do not connect within the package. These unconnected pins

can be left unconnected externally, or can be connected to

the VCCO voltage to permit migration to a larger device if

necessary.

In TQ144 and PQ/HQ240 packages, all VCCO pins are

bonded together internally, and consequently the same

VCCO voltage must be connected to all of them. In the

CS144 package, bank pairs that share a side are intercon-

nected internally, permitting four choices for VCCO. In both

cases, the VREF pins remain internally connected as eight

banks, and can be used as described previously.

Configurable Logic Block

The basic building block of the Virtex CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

Figure 5 shows a more detailed view of a single slice.

In addition to the four basic LCs, the Virtex CLB contains

logic that combines function generators to provide functions

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

Look-Up Tables

Virtex function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16x1-bit dual-port synchronous RAM.

The Virtex LUT can also provide a 16-bit shift register that is

ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

Storage Elements

The storage elements in the Virtex slice can be configured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D inputs can be driven either by the func-

tion generators within the slice or directly from slice inputs,

bypassing the function generators.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the configuration. BY forces it into the opposite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently invertible, and are shared by the two flip-flops within

the slice.

COUT

Y G4

LUT

Carry &

Control

LUT

Carry &

Control

X F4

LUT

Carry &

Control

XQ F2

LUT

Carry &

Control

Slice 1

Slice 0

CIN

Figure 4: 2-Slice Virtex CLB

slice_b.eps

Module 2 of 4

www.xilinx.com

1-800-255-7778

DS003-2 (v2.8.1) December 9, 2002

Product Specification

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