DS003-1 Datasheet, PDF (20/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
3. At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this has happened.
4. Repeat steps 2 and 3 until all the data has been sent.
5. De-assert CS and WRITE.
A flowchart for the write operation appears in Figure 17.
Note that if CCLK is slower than f_CCNH, the FPGA never
asserts BUSY. In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
CCLK
CS
WRITE
DATA[0:7]
BUSY
3
4
5
6
1
2
7
Write
Write No Write
Figure 16: Write Operations
Write
ds003_16_071902
Module 2 of 4
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DS003-2 (v2.8.1) December 9, 2002
Product Specification