DS003-1 Datasheet, PDF (52/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name
Device
CS144
TQ144
V_REF, Bank 3
(V_REF pins are listed
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
Within each bank, if
input reference voltage
is not required, all
V_REF pins are general
I/O.
XCV50
XCV100/150
XCV200/300
XCV400
XCV600
XCV800
H11, K12
... + J10
N/A
N/A
N/A
N/A
60, 68
... + 66
N/A
N/A
N/A
N/A
V_REF, Bank 4
(V_REF pins are listed
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
Within each bank, if
input reference voltage
is not required, all
V_REF pins are general
I/O.
XCV50
XCV100/150
XCV200/300
XCV400
XCV600
XCV800
L8, L10
... + N10
N/A
N/A
N/A
N/A
79, 87
... + 81
N/A
N/A
N/A
N/A
V_REF, Bank 5
(V_REF pins are listed
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
Within each bank, if
input reference voltage
is not required, all
V_REF pins are general
I/O.
XCV50
XCV100/150
XCV200/300
XCV400
XCV600
XCV800
L4, L6
... + N4
N/A
N/A
N/A
N/A
96, 104
... + 102
N/A
N/A
N/A
N/A
R
PQ/HQ240
130, 144
... + 133
... + 126
... + 147
... + 132
... + 140
97, 111
... + 108
... + 115
... + 94
... + 109
... + 101
70, 84
... + 73
... + 66
... + 87
... + 72
... + 80
Module 4 of 4
4
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DS003-4 (v2.8) July 19, 2002
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