DS003-1 Datasheet, PDF (40/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Block RAM Switching Characteristics
Speed Grade
Description
Symbol
Min
-6
-5
-4
Units
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times before/after Clock CLK⁽¹⁾
T_BCKO
1.7
3.4
3.8
4.3 ns, max
Setup Time / Hold Time
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
T_BACK/T_BCKA
T_BDCK/T_BCKD
T_BECK/T_BCKE
T_BRCK/T_BCKR
T_BWCK/T_BCKW
0.6 / 0
0.6 / 0
1.3 / 0
1.3 / 0
1.2 / 0
1.2 / 0
1.2 / 0
2.6 / 0
2.5 / 0
2.3 / 0
1.3 / 0
1.3 / 0
3.0 / 0
2.7 / 0
2.6 / 0
1.5 / 0
1.5 / 0
3.4 / 0
3.2 / 0
3.0 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
Minimum Pulse Width, High
T_BPWH
0.8
1.5
1.7
2.0 ns, min
Minimum Pulse Width, Low
T_BPWL
0.8
1.5
1.7
2.0 ns, min
CLKA -> CLKB setup time for different ports
T_BCCS
3.0
3.5
4.0 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
TBUF Switching Characteristics
Description
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
Symbol
T_IO
T_OFF
T_ON
JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Symbol
T_TAPTCK
T_TCKTAP
T_TCKTDO
F_TCK
Speed Grade
Min
-6
-5
-4
Units
0
0
0
0
ns, max
0.05 0.09 0.10 0.11 ns, max
0.05 0.09 0.10 0.11 ns, max
Speed Grade
-6
-5
-4
4.0
4.0
4.0
2.0
2.0
2.0
11.0
11.0
11.0
33
33
33
Units
ns, min
ns, min
ns, max
MHz, max
Module 3 of 4
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DS003-3 (v3.2) September 10, 2002
Production Product Specification