DS003-1 Datasheet, PDF (65/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
Pinout Diagrams
The following diagrams, CS144 Pin Function Diagram,
page 17 through FG680 Pin Function Diagram, page 27,
illustrate the locations of special-purpose pins on Virtex
FPGAs. Table 5 lists the symbols used in these diagrams.
The diagrams also show I/O-bank boundaries.
Table 5: Pinout Diagram Symbols
Symbol
Pin Function
✳
General I/O
❄
Device-dependent general I/O, n/c on
smaller devices
V
V_CCINT
v
Device-dependent V_CCINT, n/c on smaller
devices
O
V_CCO
R
V_REF
r
Device-dependent V_REF, remains I/O on
smaller devices
G
Ground
Ø, 1, 2, 3 Global Clocks
Table 5: Pinout Diagram Symbols (Continued)
Symbol
Pin Function
❿, ❶, ❷ M0, M1, M2
➉, ➀, ➁,
➂,
➃, ➄, ➅, ➆
D0/DIN, D1, D2, D3, D4, D5, D6, D7
B
DOUT/BUSY
D
DONE
P
PROGRAM
I
INIT
K
CCLK
W
WRITE
S
CS
T
Boundary-scan Test Access Port
+
Temperature diode, anode
–
Temperature diode, cathode
n
No connect
CS144 Pin Function Diagram
Bank 0
Bank 1
Bank 7
Bank 6
A GO✳✳✳ 3 2 ✳VR T TO A
B TO✳ r ✳V✳RG✳GOK B
C ✳ ✳ T R V ✳G ✳ ✳WB_➉ ✳ C
D ✳ r ✳RGRO✳ r SR✳ r D
E R✳✳G
➀^{G➁✳ E}
F
G
H
G
✳
✳
✳
O
R
✳
V
✳
✳ _CS144
✳✳_{(Top view)}
R
G
✳
➂
O
R
✳
V
➃
✳
✳
✳
F
G
H
J G✳ r ✳
r ➅G➄ J
K R✳✳✳✳✳Ø✳✳_➆✳R✳ K
L ✳❶GRGRGRGR✳P I L
M ❿O✳✳V✳ 1 ✳V✳✳DO M
N O❷✳ r ✳VO✳✳ r ✳GO N
Bank 2
Bank 3
Bank 5
Bank 4
Figure 1: CS144 Pin Function Diagram
DS003-4 (v2.8) July 19, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
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