DS003-1 Datasheet, PDF (18/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
On power-up, the CCLK frequency is 2.5 MHz. This fre-
quency is used until the ConfigRate bits have been loaded
when the frequency changes to the selected ConfigRate.
Unless a different frequency is specified in the design, the
default ConfigRate is 4 MHz.
Figure 12 shows a full master/slave system. In this system,
the left-most device operates in master-serial mode. The
remaining devices operate in slave-serial mode. The
SPROM RESET pin is driven by INIT, and the CE input is
driven by DONE. There is the potential for contention on the
DONE pin, depending on the start-up sequence options
chosen.
Figure 14 shows the timing of master-serial configuration.
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0). Table 8 shows the timing informa-
tion for Figure 14.
CCLK
(Output)
Serial Data In
TCKDS ₂
1 TDSCK
Serial DOUT
(Output)
DS022_44_071201
Figure 14: Master-Serial Mode Programming Switching Characteristics
At power-up, V_CC must rise from 1.0 V to V_CC min in less
than 50 ms, otherwise delay configuration by pulling
PROGRAM Low until V_CC is valid.
The sequence of operations necessary to configure a Virtex
FPGA serially appears in Figure 15.
SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.
An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.
Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.
In the SelectMAP mode, multiple Virtex devices can be
chained in parallel. DATA pins (D7:D0), CCLK, WRITE,
BUSY, PROGRAM, DONE, and INIT can be connected in
parallel between all the FPGAs. Note that the data is orga-
nized with the MSB of each byte on pin DO and the LSB of
each byte on D7. The CS pins are kept separate, insuring
that each FPGA can be selected individually. WRITE should
be Low before loading the first bitstream and returned High
after the last device has been programmed. Use CS to
select the appropriate FPGA for loading the bitstream and
sending the configuration data. at the end of the bitstream,
deselect the loaded device and select the next target FPGA
by setting its CS pin High. A free-running oscillator or other
externally generated signal can be used for CCLK. The
BUSY signal can be ignored for frequencies below 50 MHz.
For details about frequencies above 50 MHz, see
XAPP138, Virtex Configuration and Readback. Once all the
devices have been programmed, the DONE pin goes High.
Module 2 of 4
14
www.xilinx.com
1-800-255-7778
DS003-2 (v2.8.1) December 9, 2002
Product Specification