DS003-1 Datasheet, PDF (24/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Date
01/00
03/00
05/00
05/00
09/00
10/00
04/01
07/19/01
07/19/02
09/10/02
12/09/02
Version
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
Revision
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
Modified “Pins not listed ...” statement. Speed grade update to Final status.
Modified Table 18.
• Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
• Corrected Units column in table under IOB Input Switching Characteristics.
• Added values to table under CLB SelectRAM Switching Characteristics.
• Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
• Corrected BG256 Pin Function Diagram.
• Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
• Updated SelectMAP Write Timing Characteristics values in Table 9.
• Converted file to modularized format. See the Virtex Data Sheet section.
• Made minor edits to text under Configuration.
• Made minor edit to Figure 16 and Figure 18.
• Added clarifications in the Configuration, Boundary-Scan Mode, and Block
SelectRAM sections. Revised Figure 17.
• Added clarification in the Boundary Scan section.
• Corrected number of buffered Hex lines listed in General Purpose Routing section.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
• DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
• DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
• DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
• DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
Module 2 of 4
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DS003-2 (v2.8.1) December 9, 2002
Product Specification