DS003-1 Datasheet, PDF (51/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V Field Programmable Gate Arrays
Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name
Device
CS144
TQ144
V_CCO
All
Banks 0 and 1:
No I/O Banks in this
A2, A13, D7
package:
Banks 2 and 3:
B12, G11, M13
1, 17, 37, 55, 73, 92,
109, 128
Banks 4 and 5:
N1, N7, N13
Banks 6 and 7:
B2, G2, M2
V_REF, Bank 0
(V_REF pins are listed
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
Within each bank, if
input reference voltage
is not required, all
V_REF pins are general
I/O.
XCV50
XCV100/150
XCV200/300
XCV400
XCV600
XCV800
C4, D6
... + B4
N/A
N/A
N/A
N/A
5, 13
... + 7
N/A
N/A
N/A
N/A
V_REF, Bank 1
(V_REF pins are listed
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
Within each bank, if
input reference voltage
is not required, all
V_REF pins are general
I/O.
XCV50
XCV100/150
XCV200/300
XCV400
XCV600
XCV800
A10, B8
... + D9
N/A
N/A
N/A
N/A
22, 30
... + 28
N/A
N/A
N/A
N/A
V_REF, Bank 2
(V_REF pins are listed
incrementally. Connect
all pins listed for both
the required device
and all smaller devices
listed in the same
package.)
Within each bank, if
input reference voltage
is not required, all
V_REF pins are general
I/O.
XCV50
XCV100/150
XCV200/300
XCV400
XCV600
XCV800
D11, F10
... + D13
N/A
N/A
N/A
N/A
42, 50
... + 44
N/A
N/A
N/A
N/A
PQ/HQ240
No I/O Banks in this
package:
15, 30, 44, 61, 76, 90,
105, 121, 136, 150, 165,
180, 197, 212, 226, 240
218, 232
... + 229
... + 236
... + 215
... + 230
... + 222
191, 205
... + 194
... + 187
... + 208
... + 193
... + 201
157, 171
... + 168
... + 175
... + 154
... + 169
... + 161
DS003-4 (v2.8) July 19, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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