DS003-1 Datasheet, PDF (16/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
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Configuration
Virtex devices are configured by loading configuration data
into the internal configuration memory. Some of the pins
used for this are dedicated configuration pins, while others
can be re-used as general purpose inputs and outputs once
configuration is complete.
The following are dedicated pins:
• Mode pins (M2, M1, M0)
• Configuration clock pin (CCLK)
• PROGRAM pin
• DONE pin
• Boundary-scan pins (TDI, TDO, TMS, TCK)
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or it can be generated
externally and provided to the FPGA as an input. The
PROGRAM pin must be pulled High prior to reconfiguration.
Note that some configuration pins can act as outputs. For
correct operation, these pins can require a V_CCO of 3.3 V to
permit LVTTL operation. All the pins affected are in banks 2
or 3. The configuration pins needed for SelectMap (CS,
Write) are located in bank 1.
After Virtex devices are configured, unused IOBs function
as 3-state OBUFTs with weak pull downs. For a more
detailed description than that given below, see the
XAPP138, Virtex Configuration and Readback.
Configuration Modes
Virtex supports the following four configuration modes.
• Slave-serial mode
• Master-serial mode
• SelectMAP mode
• Boundary-scan mode
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in Table 7.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected. However, it is recom-
mended to drive the configuration mode pins externally.
Table 7: Configuration Codes
Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial D_out
Master-serial mode
000
Out
1
Yes
Boundary-scan mode 1 0 1
N/A
1
No
SelectMAP mode
110
In
8
No
Slave-serial mode
111
In
1
Yes
Master-serial mode
100
Out
1
Yes
Boundary-scan mode 0 0 1
N/A
1
No
SelectMAP mode
010
In
8
No
Slave-serial mode
011
In
1
Yes
Configuration Pull-ups
No
No
No
No
Yes
Yes
Yes
Yes
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be setup
at the DIN input pin a short time before each rising edge of
an externally generated CCLK.
For more information on serial PROMs, see the PROM data
sheet at:
http://www.xilinx.com/bvdocs/publications/ds026.pdf.
Multiple FPGAs can be daisy-chained for configuration from a
single source. After a particular FPGA has been configured,
the data for the next device is routed to the DOUT pin. The
data on the DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families, but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex-only chains.
Figure 12 shows a full master/slave system. A Virtex device
in slave-serial mode should be connected as shown in the
third device from the left.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected. However, it is recommended to drive the con-
figuration mode pins externally. Figure 13 shows
slave-serial mode programming switching characteristics.
Table 8 provides more detail about the characteristics
shown in Figure 13. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Module 2 of 4
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DS003-2 (v2.8.1) December 9, 2002
Product Specification