DS003-1 Datasheet, PDF (23/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V Field Programmable Gate Arrays
Data Stream Format
Virtex devices are configured by sequentially loading
frames of data. Table 11 lists the total number of bits
required to configure each device. For more detailed infor-
mation, see application note XAPP151 “Virtex Configura-
tion Architecture Advanced Users Guide”.
Table 11: Virtex Bit-Stream Lengths
Device
# of Configuration Bits
XCV50
559,200
XCV100
781,216
XCV150
1,040,096
XCV200
1,335,840
XCV300
1,751,808
XCV400
2,546,048
XCV600
3,607,968
XCV800
4,715,616
XCV1000
6,127,744
Readback
The configuration data stored in the Virtex configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUTRAMs, and block RAMs. This capabil-
ity is used for real-time debugging.
For more detailed information, see Application Note
XAPP138: Virtex FPGA Series Configuration and Readback,
available online at www.xilinx.com.
Revision History
Date
11/98
01/99
02/99
05/99
05/99
07/99
09/99
01/00
Version
1.0
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Revision
Initial Xilinx release.
Updated package drawings and specs.
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T_IJITCC parameter, changed T_OJIT to T_OPHASE.
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V_CCO in CS144 package on p.43.
DS003-2 (v2.8.1) December 9, 2002
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
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