DS003-1 Datasheet, PDF (10/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Each block SelectRAM cell, as illustrated in Figure 6, is a
fully synchronous dual-ported 4096-bit RAM with indepen-
dent control signals for each port. The data widths of the
two ports can be configured independently, providing
built-in bus-width conversion.
RAMB4_S#_S#
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOB[#:0]
xcv_ds_006
Figure 6: Dual-Port Block SelectRAM
Table 4 shows the depth and width aspect ratios for the
block SelectRAM.
Table 4: Block SelectRAM Port Aspect Ratios
Width Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0> DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0> DATA<15:0>
The Virtex block SelectRAM also includes dedicated routing
to provide an efficient interface with both CLBs and other
block SelectRAMs. Refer to XAPP130 for block SelectRAM
timing waveforms.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex routing archi-
tecture and its place-and-route software were defined in a
single optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
To Adjacent
GRM
To Adjacent
GRM
GRM
To Adjacent
GRM
X8794b
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
CLB
Direct Connection
To Adjacent
CLB
Figure 7: Virtex Local Routing
Local Routing
The VersaBlock provides local routing resources, as shown
in Figure 7, providing the following three types of connec-
tions.
• Interconnections among the LUTs, flip-flops, and GRM
• Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
• Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.
Module 2 of 4
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DS003-2 (v2.8.1) December 9, 2002
Product Specification