DS003-1 Datasheet, PDF (7/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V Field Programmable Gate Arrays
Input Path
A buffer In the Virtex IOB input path routes the input signal
either directly to internal logic or through an optional input
flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V_REF. The need to supply V_REF imposes
constraints on which standards can used in close proximity
to each other. See I/O Banking, page 3.
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 kΩ – 100 kΩ.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied V_CCO voltage. The need
to supply V_CCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
ing, page 3.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V_REF voltage must
be provided if the signalling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require V_CCO
and/or V_REF voltages. These voltages externally and con-
nected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
multiple V_CCO pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Bank 0
Bank 1
GCLK3 GCLK2
Virtex
Device
GCLK1 GCLK0
Bank 5
Bank 4
X8778_b
Figure 3: Virtex I/O Banks
Within a bank, output standards can be mixed only if they
use the same V_CCO. Compatible standards are shown in
Table 2. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on V_CCO.
Table 2: Compatible Output Standards
V_CCO
3.3 V
Compatible Standards
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+
2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold
voltage, V_REF. In this case, certain user-I/O pins are auto-
matically configured as inputs for the V_REF voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
The V_REF pins within a bank are interconnected internally
and consequently only one V_REF voltage can be used within
each bank. All V_REF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Within a bank, inputs that require V_REF can be mixed with
those that do not. However, only one V_REF voltage can be
used within a bank. Input buffers that use V_REF are not 5 V
tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V
tolerant.
The V_CCO and V_REF pins for each bank appear in the device
Pinout tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of V_REF and V_CCO pins
can vary depending on the size of device. In larger devices,
DS003-2 (v2.8.1) December 9, 2002
Product Specification
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