DS003-1 Datasheet, PDF (5/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V
Field Programmable Gate Arrays
DS003-2 (v2.8.1) December 9, 2002
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Architectural Description
Virtex Array
The Virtex user-programmable gate array, shown in
Figure 1, comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks
(IOBs).
• CLBs provide the functional elements for constructing
logic
• IOBs provide the interface between the package pins
and the CLBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex architecture also includes the following circuits
that connect to the GRM.
• Dedicated block memories of 4096 bits each
• Clock DLLs for clock-distribution delay compensation
and clock domain control
• 3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex IOB, Figure 2, features SelectIO™ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see Table 1.
The three IOB storage elements function either as edge-trig-
gered D-type flip-flops or as level sensitive latches. Each
IOB has a clock signal (CLK) shared by the three flip-flops
and independent clock enable signals for each flip-flop.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
The output buffer and all of the IOB control signals have
independent polarity controls.
DLL
IOBs
DLL
VersaRing
CLBs
VersaRing
IOBs
DLL
DLL
vao_b.eps
Figure 1: Virtex Architecture Overview
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Two
forms of over-voltage protection are provided, one that per-
mits 5 V compliance, and one that does not. For 5 V compli-
ance, a Zener-like structure connected to ground turns on
when the output rises to approximately 6.5 V. When PCI
3.3 V compliance is required, a conventional clamp diode is
connected to the output supply voltage, V_CCO.
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each pad. Prior to con-
figuration, all pins not involved in configuration are forced
into their high-impedance state. The pull-down resistors and
the weak-keeper circuits are inactive, but inputs can option-
ally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will float.
Consequently, external pull-up or pull-down resistors must
be provided on pins required to be at a well-defined logic
level prior to configuration.
All Virtex IOBs support IEEE 1149.1-compatible boundary
scan testing.
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DS003-2 (v2.8.1) December 9, 2002
Product Specification
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