DS003-1 Datasheet, PDF (21/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
FPGA starts to clear
configuration memory.
FPGA makes a final
clearing pass and releases
INIT when finished.
Apply Power
PROGRAM
No
from Low
to High
Yes
Release INIT
If used to delay
configuration
INIT? ^Low
High
Set WRITE = Low
Enter Data Source
Sequence A
Set CS = Low
On first FPGA
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
If no errors,
first FPGAs enter start-up phase
releasing DONE.
Apply Configuration Byte
High
Busy?
Low
End of Data? ^No
Yes
Set CS = High
On first FPGA
If no errors,
later FPGAs enter start-up phase
releasing DONE.
Repeat Sequence A For any other FPGAs
Disable Data Source
When all DONE pins
are released, DONE goes High
and start-up sequences complete.
Set WRITE = High
Configuration Completed
Figure 17: SelectMAP Flowchart for Write Operation
ds003_17_090602
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device will remain
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 18.
DS003-2 (v2.8.1) December 9, 2002
Product Specification
www.xilinx.com
1-800-255-7778
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