DS003-1 Datasheet, PDF (50/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
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Virtex Pinout Information
Pinout Tables
See www.xilinx.com for updates or additional pinout information. For convenience, Table 2, Table 3 and Table 4 list the
locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on the
device/package combination. See the Pinout Diagrams starting on page 17 for any pins not listed for a particular
part/package combination.
Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages)
Pin Name
Device
CS144
TQ144
GCK0
All
K7
90
GCK1
All
M7
93
GCK2
All
A7
19
GCK3
All
A6
16
M0
All
M1
110
M1
All
L2
112
M2
All
N2
108
CCLK
All
B13
38
PROGRAM
All
L12
72
DONE
All
M12
74
INIT
All
L13
71
BUSY/DOUT
All
C11
39
D0/DIN
All
C12
40
D1
All
E10
45
D2
All
E12
47
D3
All
F11
51
D4
All
H12
59
D5
All
J13
63
D6
All
J11
65
D7
All
K10
70
WRITE
All
C10
32
CS
All
D10
33
TDI
All
A11
34
TDO
All
A12
36
TMS
All
B1
143
TCK
All
C3
2
V_CCINT
All
A9, B6, C5, G3,
10, 15, 25, 57, 84, 94,
G12, M5, M9, N6 99, 126
PQ/HQ240
92
89
210
213
60
58
62
179
122
120
123
178
177
167
163
156
145
138
134
124
185
184
183
181
2
239
16, 32, 43, 77, 88, 104,
137, 148, 164, 198,
214, 225
Module 4 of 4
2
www.xilinx.com
1-800-255-7778
DS003-4 (v2.8) July 19, 2002
Production Product Specification