DS003-1 Datasheet, PDF (42/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Minimum Clock-to-Out for Virtex Devices
With DLL
Without DLL
I/O Standard All Devices V50 V100 V150 V200 V300 V400 V600 V800 V1000 Units
*LVTTL_S2
5.2
6.0 6.0 6.0 6.0 6.1 6.1 6.1 6.1
6.1
ns
*LVTTL_S4
3.5
4.3 4.3 4.3 4.3 4.4 4.4 4.4 4.4
4.4
ns
*LVTTL_S6
2.8
3.6 3.6 3.6 3.6 3.7 3.7 3.7 3.7
3.7
ns
*LVTTL_S8
2.2
3.1 3.1 3.1 3.1 3.1 3.1 3.2 3.2
3.2
ns
*LVTTL_S12
2.0
2.9 2.9 2.9 2.9 2.9 2.9 3.0 3.0
3.0
ns
*LVTTL_S16
1.9
2.8 2.8 2.8 2.8 2.8 2.8 2.9 2.9
2.9
ns
*LVTTL_S24
1.8
2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.7
2.8
ns
*LVTTL_F2
2.9
3.8 3.8 3.8 3.8 3.8 3.8 3.9 3.9
3.9
ns
*LVTTL_F4
1.7
2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7
2.7
ns
*LVTTL_F6
1.2
2.0 2.0 2.0 2.1 2.1 2.1 2.1 2.1
2.2
ns
*LVTTL_F8
1.1
1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0
2.0
ns
*LVTTL_F12
1.0
1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9
1.9
ns
*LVTTL_F16
0.9
1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9
1.9
ns
*LVTTL_F24
0.9
1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8
1.9
ns
LVCMOS2
1.1
1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0
2.1
ns
PCI33_3
1.5
2.4 2.4 2.4 2.4 2.4 2.4 2.5 2.5
2.5
ns
PCI33_5
1.4
2.2 2.2 2.3 2.3 2.3 2.3 2.3 2.3
2.4
ns
PCI66_3
1.1
1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1
2.1
ns
GTL
1.6
2.5 2.5 2.5 2.5 2.5 2.5 2.6 2.6
2.6
ns
GTL+
1.7
2.5 2.5 2.6 2.6 2.6 2.6 2.6 2.6
2.7
ns
HSTL I
1.1
1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0
2.0
ns
HSTL III
0.9
1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.8
1.9
ns
HSTL IV
0.8
1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7
1.8
ns
SSTL2 I
0.9
1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8
1.8
ns
SSTL2 II
0.8
1.6 1.6 1.6 1.6 1.7 1.7 1.7 1.7
1.7
ns
SSTL3 I
0.8
1.6 1.7 1.7 1.7 1.7 1.7 1.7 1.8
1.8
ns
SSTL3 II
0.7
1.5 1.5 1.6 1.6 1.6 1.6 1.6 1.6
1.7
ns
CTT
1.0
1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9
2.0
ns
AGP
1.0
1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9
2.0
ns
*S = Slow Slew Rate, F = Fast Slew Rate
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 3. In all cases, an 8 pF external capacitive
load is used.
Module 3 of 4
18
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DS003-3 (v3.2) September 10, 2002
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