DS003-1 Datasheet, PDF (37/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
Description
Symbol
Min
-6
-5
-4
Units
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
Incremental delay routing through transparent latch
to XQ/YQ outputs
T_ILO
T_IF5
T_IF5X
T_IF6Y
T_F5INY
T_IFNCTL
0.29
0.6
0.7
0.8 ns, max
0.32
0.7
0.8
0.9 ns, max
0.36
0.8
0.8
1.0 ns, max
0.44
0.9
1.0
1.2 ns, max
0.17 0.32 0.36 0.42 ns, max
0.31
0.7
0.7
0.8 ns, max
BY input to YB output
Sequential Delays
T_BYYB
0.27 0.53 0.6
0.7 ns, max
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times before/after Clock CLK⁽¹⁾
T_CKO
T_CKLO
0.54
1.1
1.2
0.6
1.2
1.4
Setup Time / Hold Time
1.4 ns, max
1.6 ns, max
4-input function: F/G Inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
T_ICK/T_CKI
T_IF5CK/T_CKIF5
T_F5INCK/T_CKF5IN
T_IF6CK/T_CKIF6
T_DICK/T_CKDI
T_CECK/T_CKCE
T_RCKT_CKR
0.6 / 0
0.7 / 0
0.46 / 0
0.8 / 0
0.30 / 0
0.37 / 0
0.33 / 0
1.2 / 0
1.3 / 0
1.0 / 0
1.5 / 0
0.6 / 0
0.8 / 0
0.7 / 0
1.4 / 0
1.5 / 0
1.1 / 0
1.7 / 0
0.7 / 0
0.9 / 0
0.8 / 0
1.5 / 0
1.7 / 0
1.2 / 0
1.9 / 0
0.8 / 0
1.0 / 0
0.9 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
T_CH
0.8
1.5
1.7
2.0 ns, min
T_CL
0.8
1.5
1.7
2.0 ns, min
Minimum Pulse Width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
T_RPW
T_RQ
1.3
2.5
2.8
3.3 ns, min
0.54
1.1
1.3
1.4 ns, max
Delay from GSR to XQ/YQ outputs
T_IOGSRQ
4.9
9.7
10.9 12.5 ns, max
Toggle Frequency (MHz) (for export control)
F_TOG (MHz)
625
333
294
250
MHz
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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