LM3S5D91 Datasheet, PDF (933/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the Host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint
0. The endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also
be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and
allow filling the other half of the FIFO.
If operating as a Device, the USB Device controller's soft connect must be enabled when the Device
is ready to start communications, indicating to the Host controller that the Device is ready to start
the enumeration process. If operating as a Host controller, the Device soft connect must be disabled
and power must be provided to VBUS via the USB0EPEN signal.
18.5
Register Map
Table 18-6 on page 933 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 280). There must be a delay of 3 system clocks after the USB module clock
is enabled before any USB module registers are accessed.
Table 18-6. Universal Serial Bus (USB) Controller Register Map
Offset Name
Type
Reset
Description
0x000 USBFADDR
0x001 USBPOWER
0x002 USBTXIS
0x004 USBRXIS
0x006 USBTXIE
0x008 USBRXIE
0x00A USBIS
0x00B USBIE
0x00C USBFRAME
0x00E USBEPIDX
0x00F USBTEST
0x020 USBFIFO0
0x024 USBFIFO1
R/W
0x00
USB Device Functional Address
R/W
0x20
USB Power
RO
0x0000
USB Transmit Interrupt Status
RO
0x0000
USB Receive Interrupt Status
R/W
0xFFFF
USB Transmit Interrupt Enable
R/W
0xFFFE
USB Receive Interrupt Enable
RO
0x00
USB General Interrupt Status
R/W
0x06
USB Interrupt Enable
RO
0x0000
USB Frame Value
R/W
0x00
USB Endpoint Index
R/W
0x00
USB Test Mode
R/W
0x0000.0000 USB FIFO Endpoint 0
R/W
0x0000.0000 USB FIFO Endpoint 1
See
page
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January 22, 2012
933
Texas Instruments-Production Data