LM3S5D91 Datasheet, PDF (731/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
Type RO
RO
RO
Reset
0
0
0
15
14
13
LME5IC LME1IC LMSBIC
Type
Reset
W1C
0
W1C
0
W1C
0
RO
RO
0
0
12
11
reserved
RO
RO
0
0
26
RO
0
10
OEIC
W1C
0
25
RO
0
9
BEIC
W1C
0
24
23
reserved
RO
RO
0
0
8
PEIC
W1C
0
7
FEIC
W1C
0
22
RO
0
6
RTIC
W1C
0
21
RO
0
5
TXIC
W1C
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RXIC DSRMIC DCDMIC CTSMIC RIMIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
31:16
15
14
13
12:11
10
9
8
Name
reserved
LME5IC
LME1IC
LMSBIC
reserved
OEIC
BEIC
PEIC
Type
RO
W1C
W1C
W1C
RO
W1C
W1C
W1C
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Interrupt Clear
Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register
and the LME5MIS bit in the UARTMIS register.
LIN Mode Edge 1 Interrupt Clear
Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register
and the LME1MIS bit in the UARTMIS register.
LIN Mode Sync Break Interrupt Clear
Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register
and the LMSBMIS bit in the UARTMIS register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
January 22, 2012
731
Texas Instruments-Production Data