LM3S5D91 Datasheet, PDF (693/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
13.3.7
The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in
Table 13-3 on page 693.
Table 13-3. Flow Control Mode
CTSEN
1
1
0
0
RTSEN
1
0
1
0
Description
RTS and CTS flow control enabled
Only CTS flow control enabled
Only RTS flow control enabled
Both RTS and CTS flow control disabled
Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL
register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status
of the UART. Interrupts may be generated for the U1DSR, U1DCD, U1CTS, and U1RI signals using
bits 3:0 of the UARTIM register, respectively. The raw and masked interrupt status may be checked
using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR
register.
LIN Support
The UART module offers hardware support for the LIN protocol as either a master or a slave. The
LIN mode is enabled by setting the LIN bit in the UARTCTL register. A LIN message is identified
by the use of a Sync Break at the beginning of the message. The Sync Break is a transmission of
a series of 0s. The Sync Break is followed by the Sync data field (0x55). Figure 13-4 on page 693
illustrates the structure of a LIN message.
Figure 13-4. LIN Message
Message Frame
Synch
Break
Header
Synch Field Ident Field
Data
Field(s)
Response
Data Field
Checksum
Field
In-Frame
Response
Interbyte
Space
The UART should be configured as followed to operate in LIN mode:
1. Configure the UART for 1 start bit, 8 data bits, no parity, and 1 stop bit. Enable the Transmit
FIFO.
2. Set the LIN bit in the UARTCTL register.
January 22, 2012
693
Texas Instruments-Production Data