LM3S5D91 Datasheet, PDF (9/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
20 Pulse Width Modulator (PWM) .......................................................................... 1070
20.1 Block Diagram ........................................................................................................... 1071
20.2 Signal Description ..................................................................................................... 1072
20.3 Functional Description ............................................................................................... 1075
20.3.1 PWM Timer ............................................................................................................... 1075
20.3.2 PWM Comparators .................................................................................................... 1076
20.3.3 PWM Signal Generator .............................................................................................. 1077
20.3.4 Dead-Band Generator ............................................................................................... 1078
20.3.5 Interrupt/ADC-Trigger Selector ................................................................................... 1078
20.3.6 Synchronization Methods .......................................................................................... 1079
20.3.7 Fault Conditions ........................................................................................................ 1080
20.3.8 Output Control Block .................................................................................................. 1080
20.4 Initialization and Configuration .................................................................................... 1081
20.5 Register Map ............................................................................................................ 1082
20.6 Register Descriptions ................................................................................................. 1085
21 Quadrature Encoder Interface (QEI) ................................................................. 1148
21.1 Block Diagram ........................................................................................................... 1148
21.2 Signal Description ..................................................................................................... 1149
21.3 Functional Description ............................................................................................... 1150
21.4 Initialization and Configuration .................................................................................... 1153
21.5 Register Map ............................................................................................................ 1153
21.6 Register Descriptions ................................................................................................. 1154
22 Pin Diagram ........................................................................................................ 1171
23 Signal Tables ...................................................................................................... 1173
23.1 100-Pin LQFP Package Pin Tables ............................................................................. 1174
23.2 108-Ball BGA Package Pin Tables .............................................................................. 1212
23.3 Connections for Unused Signals ................................................................................. 1251
24 Operating Characteristics ................................................................................. 1253
25 Electrical Characteristics .................................................................................. 1254
25.1 Maximum Ratings ...................................................................................................... 1254
25.2 Recommended Operating Conditions ......................................................................... 1254
25.3 Load Conditions ........................................................................................................ 1255
25.4 JTAG and Boundary Scan .......................................................................................... 1255
25.5 Power and Brown-Out ............................................................................................... 1257
25.6 Reset ........................................................................................................................ 1258
25.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1259
25.8 Clocks ...................................................................................................................... 1259
25.8.1 PLL Specifications ..................................................................................................... 1259
25.8.2 PIOSC Specifications ................................................................................................ 1260
25.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 1260
25.8.4 Main Oscillator Specifications ..................................................................................... 1261
25.8.5 System Clock Specification with ADC Operation .......................................................... 1262
25.8.6 System Clock Specification with USB Operation .......................................................... 1262
25.9 Sleep Modes ............................................................................................................. 1262
25.10 Flash Memory ........................................................................................................... 1262
25.11 Input/Output Characteristics ....................................................................................... 1263
25.12 External Peripheral Interface (EPI) .............................................................................. 1263
January 22, 2012
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