LM3S5D91 Datasheet, PDF (19/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
List of Registers
The Cortex-M3 Processor ............................................................................................................. 67
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 74
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 74
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 74
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 74
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 74
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 74
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 74
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 74
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 74
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 74
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 74
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 74
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 74
Register 14: Stack Pointer (SP) ........................................................................................................... 75
Register 15: Link Register (LR) ............................................................................................................ 76
Register 16: Program Counter (PC) ..................................................................................................... 77
Register 17: Program Status Register (PSR) ........................................................................................ 78
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 82
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 83
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 84
Register 21: Control Register (CONTROL) ........................................................................................... 85
Cortex-M3 Peripherals ................................................................................................................. 110
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 121
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 123
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 124
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 125
Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 126
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 127
Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 128
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 129
Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 130
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 131
Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 132
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 133
Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 134
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 135
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 135
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 135
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 135
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 135
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 135
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 135
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 135
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 135
January 22, 2012
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