LM3S5D91 Datasheet, PDF (60/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Architectural Overview
1.3.5.4
1.3.5.5
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine.
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
CCP Pins (see page 540)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The LM3S5D91 microcontroller includes eight Capture Compare PWM pins (CCP) that can be
programmed to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
Watchdog Timers (see page 579)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer can
generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog Timer
is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its
first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S5D91 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
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January 22, 2012
Texas Instruments-Production Data