LM3S5D91 Datasheet, PDF (104/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

The Cortex-M3 Processor
2.6.2
Table 2-11. Faults (continued)
Fault
Handler
Fault Status Register
Bit Name
Fault escalated to a hard fault
Hard fault
MPU or default memory mismatch on Memory management
instruction access
fault
Hard Fault Status (HFAULTSTAT)
Memory Management Fault Status
(MFAULTSTAT)
FORCED
IERR ^a
MPU or default memory mismatch on Memory management Memory Management Fault Status
data access
fault
(MFAULTSTAT)
DERR
MPU or default memory mismatch on Memory management Memory Management Fault Status
exception stacking
fault
(MFAULTSTAT)
MSTKE
MPU or default memory mismatch on Memory management Memory Management Fault Status
exception unstacking
fault
(MFAULTSTAT)
MUSTKE
Bus error during exception stacking Bus fault
Bus Fault Status (BFAULTSTAT)
BSTKE
Bus error during exception unstacking Bus fault
Bus Fault Status (BFAULTSTAT)
BUSTKE
Bus error during instruction prefetch Bus fault
Bus Fault Status (BFAULTSTAT)
IBUS
Precise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
PRECISE
Imprecise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
IMPRE
Attempt to access a coprocessor
Usage fault
Usage Fault Status (UFAULTSTAT) NOCP
Undefined instruction
Usage fault
Usage Fault Status (UFAULTSTAT) UNDEF
Attempt to enter an invalid instruction Usage fault
set state ^b
Usage Fault Status (UFAULTSTAT) INVSTAT
Invalid EXC_RETURN value
Usage fault
Usage Fault Status (UFAULTSTAT) INVPC
Illegal unaligned load or store
Usage fault
Usage Fault Status (UFAULTSTAT) UNALIGN
Divide by 0
Usage fault
Usage Fault Status (UFAULTSTAT) DIV0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.
Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 151). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 154).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 95.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
104
January 22, 2012
Texas Instruments-Production Data