LM3S5D91 Datasheet, PDF (631/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
Bit/Field
16
15:4
3
2
1
0
Name
DCONSS0
reserved
MASK3
MASK2
MASK1
MASK0
Type
R/W
RO
R/W
R/W
R/W
R/W
Reset
0
Description
Digital Comparator Interrupt on SS0
Value Description
1 The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS0 interrupt line.
0 The status of the digital comparators does not affect the SS0
interrupt status.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
SS3 Interrupt Mask
Value Description
1 The raw interrupt signal from Sample Sequencer 3 (ADCRIS
register INR3 bit) is sent to the interrupt controller.
0 The status of Sample Sequencer 3 does not affect the SS3
interrupt status.
0
SS2 Interrupt Mask
Value Description
1 The raw interrupt signal from Sample Sequencer 2 (ADCRIS
register INR2 bit) is sent to the interrupt controller.
0 The status of Sample Sequencer 2 does not affect the SS2
interrupt status.
0
SS1 Interrupt Mask
Value Description
1 The raw interrupt signal from Sample Sequencer 1 (ADCRIS
register INR1 bit) is sent to the interrupt controller.
0 The status of Sample Sequencer 1 does not affect the SS1
interrupt status.
0
SS0 Interrupt Mask
Value Description
1 The raw interrupt signal from Sample Sequencer 0 (ADCRIS
register INR0 bit) is sent to the interrupt controller.
0 The status of Sample Sequencer 0 does not affect the SS0
interrupt status.
January 22, 2012
631
Texas Instruments-Production Data