LM3S5D91 Datasheet, PDF (198/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

System Control
Using the SYSDIV and SYSDIV2 Fields
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 196.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
0x0
Divisor Frequency (BYPASS=0) Frequency (BYPASS=1)
/1 reserved
Clock source frequency/2
StellarisWare^® Parameter^a
SYSCTL_SYSDIV_1^b
0x1
/2 reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3 66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4 50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5 40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6 33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7 28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8 25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9 22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10 20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11 18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12 16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13 15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14 14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15 13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16 12.5 MHz (default) Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-4 on page 196.
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
SYSDIV2
0x00
Divisor
/1
Frequency
(BYPASS2=0)
reserved
Frequency (BYPASS2=1)
Clock source frequency/2
StellarisWare Parameter^a
SYSCTL_SYSDIV_1^b
0x01
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x02
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x03
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x04
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
198
January 22, 2012
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