LM3S5D91 Datasheet, PDF (57/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
1.3.5
1.3.5.1
– Channel requests asserted when FIFO contains required amount of data
System Integration
The LM3S5D91 microcontroller provides a variety of standard system functions integrated into the
device, including:
■ Direct Memory Access Controller (DMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ Four 32-bit timers (up to eight 16-bit), with real-time clock capability
■ Eight Capture Compare PWM (CCP) pins
■ Two Watchdog Timers
– One timer runs off the main oscillator
– One timer runs off the precision internal oscillator
■ Up to 72 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2, 4 or 8 mA drive capability
– Up to 4 GPIOs can have 18 mA drive capability
The following sections provide more detail on each of these functions.
Direct Memory Access (see page 339)
The LM3S5D91 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
■ ARM PrimeCell^® 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Primary and secondary channel assignments
– One channel each for receive and transmit path for bidirectional modules
January 22, 2012
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