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LM3S5D91 Datasheet, PDF (58/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller | |||
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Architectural Overview
1.3.5.2
â Dedicated channel for software-initiated transfers
â Per-channel configurable priority scheme
â Optional software-initiated requests for any channel
â Two levels of priority
â Design optimizations for improved bus access performance between µDMA controller and the
processor core
â µDMA controller access is subordinate to core access
â RAM striping
â Peripheral bus segmentation
â Data sizes of 8, 16, and 32 bits
â Transfer size is programmable in binary steps from 1 to 1024
â Source and destination address increment size of byte, half-word, word, or no increment
â Maskable peripheral requests
â Interrupt on transfer completion, with a separate interrupt per channel
System Control and Clocks (see page 188)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
â Device identification information: version, part number, SRAM size, Flash memory size, and so
on
â Power control
â On-chip fixed Low Drop-Out (LDO) voltage regulator
â Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating
â Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
â 3.3-V supply brown-out detection and reporting via interrupt or reset
â Multiple clock sources for microcontroller system clock
â Precision Oscillator (PIOSC): On-chip resource providing a 16 MHz ±1% frequency at room
temperature
⢠16 MHz ±3% across temperature
⢠Can be recalibrated with 7-bit trim resolution
⢠Software power down control for low power modes
58
January 22, 2012
Texas Instruments-Production Data
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