LM3S5D91 Datasheet, PDF (1018/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
3
2
1
0
Name
DMAMOD
DTWE
DT
reserved
Type
R/W
RO
RO
RO
Reset
0
0
0
0
Description
DMA Request Mode
Value Description
0 An interrupt is generated after every µDMA packet transfer.
1 An interrupt is generated only after the entire μDMA transfer is
complete.
Note: This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Data Toggle Write Enable
Value Description
0 The DT bit cannot be written.
1 Enables the current state of the receive endpoint data to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
Data Toggle
When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the
data toggle. If DTWE is Low, any value written to this bit is ignored. Care
should be taken when writing to this bit as it should only be changed to
RESET the receive endpoint.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OTG B / Device Mode
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
AUTOCL ISO
DMAEN ^{DISNYET /} DMAMOD
PIDERR
reserved
Type R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
1018
Texas Instruments-Production Data
January 22, 2012