LM3S5D91 Datasheet, PDF (539/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
Wait-for-Trigger Mode
The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured,
a single timer can initiate mulitple timing events using the Timer triggers. Wait-for-Trigger mode is
enabled by setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1
does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches
its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2
follows GPTM1, and so on. If Timer A is in 32-bit mode (controlled by the GPTMCFG bit in the
GPTMCFG register), it triggers Timer A in the next module. If Timer A is in 16-bit mode, it triggers
Timer B in the same module, and Timer B triggers Timer A in the next module. Care must be taken
that the TAWOT bit is never set in GPTM0. Figure 10-2 on page 539 shows how the GPTMCFG bit
affects the daisy chain. This function is valid for both one-shot and periodic modes.
Figure 10-2. Timer Daisy Chain
GP Timer N+1
10
GPTMCFG
Timer B
Timer A
Timer B ADC Trigger
Timer A ADC Trigger
GP Timer N
10
GPTMCFG
Timer B
Timer A
Timer B ADC Trigger
Timer A ADC Trigger
10.3.2.2
Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as an up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM
Timer A Interval Load (GPTMTAILR) register (see page 567). Table 10-7 on page 539 shows the
values that are loaded into the timer registers when the timer is enabled.
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode
Register
TnR
TnV
Count Down Mode
Not available
Not available
Count Up Mode
0x1
0x1
The input clock on a CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then
divided down to a 1-Hz rate and is passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting
until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer
value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the
RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
January 22, 2012
539
Texas Instruments-Production Data