LM3S5D91 Datasheet, PDF (12/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Table of Contents
Figure 9-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 483
Figure 9-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 484
Figure 9-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 484
Figure 9-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 484
Figure 9-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 485
Figure 9-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 485
Figure 9-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 485
Figure 9-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 485
Figure 9-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 486
Figure 9-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 487
Figure 9-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 487
Figure 10-1. GPTM Module Block Diagram ............................................................................ 533
Figure 10-2. Timer Daisy Chain ............................................................................................. 539
Figure 10-3. Input Edge-Count Mode Example ....................................................................... 541
Figure 10-4. 16-Bit Input Edge-Time Mode Example ............................................................... 542
Figure 10-5. 16-Bit PWM Mode Example ................................................................................ 543
Figure 11-1. WDT Module Block Diagram .............................................................................. 580
Figure 12-1. Implementation of Two ADC Blocks .................................................................... 605
Figure 12-2. ADC Module Block Diagram ............................................................................... 606
Figure 12-3. ADC Sample Phases ......................................................................................... 610
Figure 12-4. Doubling the ADC Sample Rate .......................................................................... 611
Figure 12-5. Skewed Sampling .............................................................................................. 611
Figure 12-6. Sample Averaging Example ............................................................................... 612
Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 613
Figure 12-8. Internal Voltage Conversion Result ..................................................................... 614
Figure 12-9. External Voltage Conversion Result with 3.0-V Setting ......................................... 615
Figure 12-10. External Voltage Conversion Result with 1.0-V Setting ......................................... 615
Figure 12-11. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 617
Figure 12-12. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 617
Figure 12-13. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 618
Figure 12-14. Internal Temperature Sensor Characteristic ......................................................... 619
Figure 12-15. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 621
Figure 12-16. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 622
Figure 12-17. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 623
Figure 13-1. UART Module Block Diagram ............................................................................. 686
Figure 13-2. UART Character Frame ..................................................................................... 689
Figure 13-3. IrDA Data Modulation ......................................................................................... 691
Figure 13-4. LIN Message ..................................................................................................... 693
Figure 13-5. LIN Synchronization Field ................................................................................... 694
Figure 14-1. SSI Module Block Diagram ................................................................................. 750
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 754
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 754
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 755
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 755
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 756
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 757
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 757
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January 22, 2012
Texas Instruments-Production Data