LM3S5D91 Datasheet, PDF (355/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
7.2.10
7.3
7.3.1
Interrupts and Errors
When a μDMA transfer is complete, the μDMA controller generates a completion interrupt on the
interrupt vector of the peripheral. Therefore, if μDMA is used to transfer data for a peripheral and
interrupts are used, then the interrupt handler for that peripheral must be designed to handle the
μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the
completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table
7-6 on page 355).
When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts
for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's
interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving
multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt
when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the
interrupt controller.
When a μDMA channel generates a completion interrupt, the CHIS bit corresponding to the peripheral
channel is set in the DMA Channel Interrupt Status (DMACHIS) register (see page 390). This
register can be used by the peripheral interrupt handler code to determine if the interrupt was caused
by the μDMA channel or an error event reported by the peripheral's interrupt registers. The completion
interrupt request from the μDMA controller is automatically cleared when the interrupt handler is
activated.
If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA
error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register
to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be
cleared by writing a 1 to the ERRCLR bit.
Table 7-6 shows the dedicated interrupt assignments for the μDMA controller.
Table 7-6. μDMA Interrupt Assignments
Interrupt
46
47
Assignment
μDMA Software Channel Transfer
μDMA Error
Initialization and Configuration
Module Initialization
Before the μDMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA
bit of the System Control RCGC2 register (see page 280).
2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the
DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be
aligned on a 1024-byte boundary.
January 22, 2012
355
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