LM3S5D91 Datasheet, PDF (27/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 771
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 772
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 773
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 775
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 777
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 778
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 779
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 780
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 781
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 782
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 783
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 784
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 785
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 786
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 787
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 788
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 789
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 790
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 791
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 808
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 809
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 814
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 815
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 816
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 817
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 818
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 819
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 820
Register 10: I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 821
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 822
Register 12: I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 824
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 825
Register 14: I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 826
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 827
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 828
Inter-Integrated Circuit Sound (I²S) Interface ............................................................................ 829
Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 842
Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 843
Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 844
Register 4: I²S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 846
Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 847
Register 6: I²S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 848
Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 849
Register 8: I²S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 850
Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 851
Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 854
January 22, 2012
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