LM3S5D91 Datasheet, PDF (15/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Revision History .................................................................................................. 39
Documentation Conventions ................................................................................ 43
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 72
Processor Register Map ....................................................................................... 73
PSR Register Combinations ................................................................................. 78
Memory Map ....................................................................................................... 86
Memory Access Behavior ..................................................................................... 89
SRAM Memory Bit-Banding Regions .................................................................... 91
Peripheral Memory Bit-Banding Regions ............................................................... 91
Exception Types .................................................................................................. 97
Interrupts ............................................................................................................ 98
Exception Return Behavior ................................................................................. 103
Faults ............................................................................................................... 103
Fault Status and Fault Address Registers ............................................................ 105
Cortex-M3 Instruction Summary ......................................................................... 107
Core Peripheral Register Regions ....................................................................... 110
Memory Attributes Summary .............................................................................. 113
TEX, S, C, and B Bit Field Encoding ................................................................... 116
Cache Policy for Memory Attribute Encoding ....................................................... 117
AP Bit Field Encoding ........................................................................................ 117
Memory Region Attributes for Stellaris Microcontrollers ........................................ 117
Peripherals Register Map ................................................................................... 118
Interrupt Priority Levels ...................................................................................... 145
Example SIZE Field Values ................................................................................ 173
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 177
JTAG_SWD_SWO Signals (108BGA) ................................................................. 178
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 179
JTAG Instruction Register Commands ................................................................. 184
System Control & Clocks Signals (100LQFP) ...................................................... 188
System Control & Clocks Signals (108BGA) ........................................................ 188
Reset Sources ................................................................................................... 189
Clock Source Options ........................................................................................ 196
Possible System Clock Frequencies Using the SYSDIV Field ............................... 198
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 198
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 199
System Control Register Map ............................................................................. 203
RCC2 Fields that Override RCC Fields ............................................................... 225
Flash Memory Protection Policy Combinations .................................................... 297
User-Programmable Flash Memory Resident Registers ....................................... 301
Flash Register Map ............................................................................................ 301
μDMA Channel Assignments .............................................................................. 341
Request Type Support ....................................................................................... 343
Control Structure Memory Map ........................................................................... 344
Channel Control Structure .................................................................................. 344
μDMA Read Example: 8-Bit Peripheral ................................................................ 354
μDMA Interrupt Assignments .............................................................................. 355
January 22, 2012
15
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