LM3S5D91 Datasheet, PDF (538/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

General-Purpose Timers
counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional
GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer
stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer,
the timer starts counting again on the next cycle.
In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is set in the GPTMTnMR
register), the value of the timer at the time-out event is loaded into the GPTMTnR register. The
free-running counter value is shown in the GPTMTnV register. In this manner, software can determine
the time elapsed from the interrupt assertion to the ISR entry by examining the snapshot values
and the current value of the free-running timer. Snapshot mode is not available when the timer is
configured in one-shot mode.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPTMRIS)
register (see page 559), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR)
register (see page 565). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR)
register (see page 557), the GPTM also sets the TnTOMIS bit in the GPTM Masked Interrupt Status
(GPTMMIS) register (see page 562). By setting the TnMIE bit in the GPTMTnMR register, an interrupt
condition can also be generated when the Timer value equals the value loaded into the GPTM Timer
n Match (GPTMTnMATCHR) and GPTM Timer n Prescale Match (GPTMTnPMR) registers. This
interrupt has the same status, masking, and clearing functions as the time-out interrupt, but uses
the match interrupt bits instead (for example, the raw interrupt status is monitored via TnMRIS bit
in the GPTM Raw Interrupt Status (GPTMRIS) register). Note that the interrupt status bits are not
updated by the hardware unless the TnMIE bit in the GPTMTnMR register is set, which is different
than the behavior for the time-out interrupt. The ADC trigger is enabled by setting the TnOTE bit in
GPTMCTL. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel.
See “Channel Configuration” on page 344.
If software updates the GPTMTnILR register while the counter is counting down, the counter loads
the new value on the next clock cycle and continues counting from the new value. If software updates
the GPTMTnILR register while the counter is counting up, the timeout event is changed on the next
cycle to the new value. If software updates the GPTM Timer n Value (GPTMTnV) register while
the counter is counting up or down, the counter loads the new value on the next clock cycle and
continues counting from the new value..
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following table shows a variety of configurations for a 16-bit free-running timer while using the
prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period). The prescaler can
only be used when a 16/32-bit timer is configured in 16-bit mode.
Table 10-6. 16-Bit Timer With Prescaler Configurations
Prescale (8-bit value)
# of Timer Clocks (Tc)^a
00000000
1
00000001
2
00000010
3
------------
--
11111101
254
11111110
255
11111111
256
a. Tc is the clock period.
Max Time
0.8192
1.6384
2.4576
--
208.0768
208.896
209.7152
Units
ms
ms
ms
--
ms
ms
ms
538
January 22, 2012
Texas Instruments-Production Data