LM3S5D91 Datasheet, PDF (13/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 758
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 759
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 760
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 760
Figure 15-1. I²C Block Diagram ............................................................................................. 792
Figure 15-2. I²C Bus Configuration ........................................................................................ 793
Figure 15-3. START and STOP Conditions ............................................................................. 794
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 794
Figure 15-5. R/S Bit in First Byte ............................................................................................ 795
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 795
Figure 15-7. Master Single TRANSMIT .................................................................................. 799
Figure 15-8. Master Single RECEIVE ..................................................................................... 800
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 801
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 802
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 803
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 804
Figure 15-13. Slave Command Sequence ................................................................................ 805
Figure 16-1. I²S Block Diagram ............................................................................................. 830
Figure 16-2. I²S Data Transfer ............................................................................................... 833
Figure 16-3. Left-Justified Data Transfer ................................................................................ 833
Figure 16-4. Right-Justified Data Transfer .............................................................................. 833
Figure 17-1. CAN Controller Block Diagram ............................................................................ 867
Figure 17-2. CAN Data/Remote Frame .................................................................................. 869
Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 877
Figure 17-4. CAN Bit Time .................................................................................................... 881
Figure 18-1. USB Module Block Diagram ............................................................................... 918
Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1057
Figure 19-2. Structure of Comparator Unit ............................................................................ 1059
Figure 19-3. Comparator Internal Reference Structure .......................................................... 1059
Figure 20-1. PWM Module Diagram ..................................................................................... 1072
Figure 20-2. PWM Generator Block Diagram ........................................................................ 1072
Figure 20-3. PWM Count-Down Mode .................................................................................. 1077
Figure 20-4. PWM Count-Up/Down Mode ............................................................................. 1077
Figure 20-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1078
Figure 20-6. PWM Dead-Band Generator ............................................................................. 1078
Figure 21-1. QEI Block Diagram .......................................................................................... 1149
Figure 21-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1152
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1171
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1172
Figure 25-1. Load Conditions ............................................................................................... 1255
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1256
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1256
Figure 25-4. Power-On Reset Timing ................................................................................... 1257
Figure 25-5. Brown-Out Reset Timing .................................................................................. 1257
Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1258
Figure 25-7. External Reset Timing (RST) ............................................................................ 1258
January 22, 2012
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Texas Instruments-Production Data