LM3S5D91 Datasheet, PDF (22/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Table of Contents
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ................................... 331
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 332
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 333
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 334
Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 335
Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 336
Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 337
Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 338
Micro Direct Memory Access (μDMA) ........................................................................................ 339
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 364
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 365
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 366
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 371
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 373
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 374
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 375
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 376
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 377
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 378
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 379
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 380
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 381
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 382
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 383
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 384
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 385
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 386
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 387
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 388
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 389
Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 390
Register 23: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 391
Register 24: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 392
Register 25: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 393
Register 26: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 394
Register 27: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 395
Register 28: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 396
Register 29: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 397
Register 30: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 398
Register 31: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 399
General-Purpose Input/Outputs (GPIOs) ................................................................................... 400
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 415
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 416
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 417
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 418
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 419
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 420
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 421
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January 22, 2012
Texas Instruments-Production Data