LM3S5D91 Datasheet, PDF (468/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

External Peripheral Interface (EPI)
9.4.1.6
Write Cycle
Figure 9-4 on page 468 shows a write cycle of n halfwords; n can be any number greater than or
equal to 1. The cycle begins with the Activate command and the row address on the EPI0S[15:0]
signals. With the programmed CAS latency of 2, the Write command with the column address on
the EPI0S[15:0] signals follows after 2 clock cycles. When writing to SDRAMs, the Write command
is presented with the first halfword of data. Because the address lines and the data lines are
multiplexed, the column address is modified to be (programmed address -1). During the Write
command, the DQMH and DQML signals are high, so no data is written to the SDRAM. On the next
clock, the DQMH and DQML signals are asserted, and the data associated with the programmed
address is written. The Burst Terminate command occurs during the clock cycle following the write
of the last halfword of data. The WEn, DQMH, DQML, and CSn signals are deasserted after the
last halfword of data is received, signaling the end of the access. At least one clock period of inactivity
separates any two SDRAM cycles.
Figure 9-4. SDRAM Write Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
NOP
AD [15:0] driven out
NOP
Column-1
Write
Data 0
Data 1
...
AD [15:0] driven out
Data n
Burst
Term
9.4.2
9.4.2.1
Host Bus Mode
Host Bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051 devices and
SRAM devices. This interface is asynchronous and uses strobe pins to control activity. Addressable
memory can be doubled using Host Bus-16 mode as it performs half-word accesses. The EPI0S0
is the LSB of the address and is equivalent to the internal Cortex-M3 A1 address. EPI0S0 should
be connected to A0 of 16-bit memories.
Control Pins
The main three strobes are Address Latch Enable (ALE), Write (WRn), and Read (RDn, sometimes
called OEn). Note that the timings are designed for older logic and so are hold-time vs. setup-time
specific. The polarity of the read and write strobes can be active High or active Low by clearing or
setting the RDHIGH and WRHIGH bits in the EPI Host-Bus n Configuration 2 (EPIHBnCFG2)
register.
The ALE can be changed to an active-low chip select signal, CSn, through the EPIHBnCFG2 register.
The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared.
All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an
468
January 22, 2012
Texas Instruments-Production Data