LM3S5D91 Datasheet, PDF (464/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

External Peripheral Interface (EPI)
9.4.1
5. Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate
pins. See page 443 and Table 23-5 on page 1206.
6. Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the
MODE field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed)
using the appropriate mode configuration EPI Host Bus Configuration (EPIHBnCFGn) registers
for the desired chip-select configuration. Set the EPI Main Baud Rate (EPIBAUD) register if
the baud rate must be slower than the system clock rate.
7. Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The
selected start address and range is dependent on the type of external device and maximum
address (as appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to
0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to
0x3 for 256 MB. If using General-Purpose mode and no address at all, program the EPADR field
to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field
to 0x0 for 256 bytes.
8. To read or write directly, use the mapped address area (configured with the EPIADDRMAP
register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked
until the value is retrieved.
9. To perform a non-blocking read, see “Non-Blocking Reads” on page 462.
The following sub-sections describe the initialization and configuration for each of the modes of
operation. Care must be taken to initialize everything properly to ensure correct operation. Control
of the GPIO states is also important, as changes may cause the external device to interpret pin
states as actions or commands (see “Register Descriptions” on page 414). Normally, a pull-up or
pull-down is needed on the board to at least control the chip-select or chip-enable as the Stellaris
GPIOs come out of reset in tri-state.
SDRAM Mode
When activating the SDRAM mode, it is important to consider a few points:
1. Generally, it takes over 100 μs from when the mode is activated to when the first operation is
allowed. The SDRAM controller begins the SDRAM initialization sequence as soon as the mode
is selected and enabled via the EPICFG register. It is important that the GPIOs are properly
configured before the SDRAM mode is enabled, as the EPI controller is relying on the GPIO
block's ability to drive the pins immediately. As part of the initialization sequence, the LOAD
MODE REGISTER command is automatically sent to the SDRAM with a value of 0x27, which
sets a CAS latency of 2 and a full page burst length.
2. The INITSEQ bit in the EPI Status (EPISTAT) register can be checked to determine when the
initialization sequence is complete.
3. When using a frequency range and/or refresh value other than the default value, it is important
to configure the FREQ and RFSH fields in the EPI SDRAM Configuration (EPISDRAMCFG)
register shortly after activating the mode. After the 100-μs startup time, the EPI block must be
configured properly to keep the SDRAM contents stable.
4. The SLEEP bit in the EPISDRAMCFG register may be configured to put the SDRAM into a
low-power self-refreshing state. It is important to note that the SDRAM mode must not be
disabled once enabled, or else the SDRAM is no longer clocked and the contents are lost.
464
January 22, 2012
Texas Instruments-Production Data