LM3S5D91 Datasheet, PDF (20/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Table of Contents
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Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 135
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 135
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 135
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 135
Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 135
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 137
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 138
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 140
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 141
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 144
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 145
System Control (SYSCTRL), offset 0xD10 ....................................................................... 147
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 149
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 151
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 152
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 153
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 154
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 158
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 164
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 165
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 166
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 167
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 168
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 170
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 171
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 171
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 171
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 171
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 173
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 173
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 173
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 173
System Control ............................................................................................................................ 188
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 206
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 208
Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 209
Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 211
Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 213
Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 215
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 217
Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 222
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 223
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 225
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 228
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 229
Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 231
Register 14: I²S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 232
Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 234
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January 22, 2012
Texas Instruments-Production Data