LM3S5D91 Datasheet, PDF (11/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
List of Figures
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Stellaris LM3S5D91 Microcontroller High-Level Block Diagram ............................... 46
CPU Block Diagram ............................................................................................. 69
TPIU Block Diagram ............................................................................................ 70
Cortex-M3 Register Set ........................................................................................ 72
Bit-Band Mapping ................................................................................................ 93
Data Storage ....................................................................................................... 94
Vector Table ...................................................................................................... 100
Exception Stack Frame ...................................................................................... 102
SRD Use Example ............................................................................................. 116
JTAG Module Block Diagram .............................................................................. 177
Test Access Port State Machine ......................................................................... 180
IDCODE Register Format ................................................................................... 186
BYPASS Register Format ................................................................................... 186
Boundary Scan Register Format ......................................................................... 187
Basic RST Configuration .................................................................................... 191
External Circuitry to Extend Power-On Reset ....................................................... 191
Reset Circuit Controlled by Switch ...................................................................... 192
Power Architecture ............................................................................................ 195
Main Clock Tree ................................................................................................ 197
Internal Memory Block Diagram .......................................................................... 293
μDMA Block Diagram ......................................................................................... 340
Example of Ping-Pong μDMA Transaction ........................................................... 347
Memory Scatter-Gather, Setup and Configuration ................................................ 349
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 350
Peripheral Scatter-Gather, Setup and Configuration ............................................. 352
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 353
Digital I/O Pads ................................................................................................. 406
Analog/Digital I/O Pads ...................................................................................... 407
GPIODATA Write Example ................................................................................. 408
GPIODATA Read Example ................................................................................. 408
EPI Block Diagram ............................................................................................. 459
SDRAM Non-Blocking Read Cycle ...................................................................... 467
SDRAM Normal Read Cycle ............................................................................... 467
SDRAM Write Cycle ........................................................................................... 468
Example Schematic for Muxed Host-Bus 16 Mode ............................................... 474
Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 476
Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 477
Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 477
Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual
CSn .................................................................................................................. 478
Continuous Read Mode Accesses ...................................................................... 478
Write Followed by Read to External FIFO ............................................................ 479
Two-Entry FIFO ................................................................................................. 479
Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 483
January 22, 2012
11
Texas Instruments-Production Data