LM3S5D91 Datasheet, PDF (465/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
9.4.1.1
5. Before entering SLEEP mode, make sure all non-blocking reads and normal reads and writes
have completed. If the system is running at 30 to 50 MHz, wait 2 EPI clocks after clearing the
SLEEP bit before executing non-blocking reads, or normal reads and writes. If the system is
configured to greater than 50 MHz, wait 5 EPI clocks before read and write transactions. For
all other configurations, wait 1 EPI clock.
The SIZE field of the EPISDRAMCFG register must be configured correctly based on the amount
of SDRAM in the system.
The FREQ field must be configured according to the value that represents the range being used.
Based on the range selected, the number of external clocks used between certain operations (for
example, PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used,
then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower
frequency is given, incorrect operation occurs.
See “External Peripheral Interface (EPI)” on page 1263 for timing details for the SDRAM mode.
External Signal Connections
Table 9-3 on page 465 defines how EPI module signals should be connected to SDRAMs. The table
applies when using a SDRAM up to 512 megabits. Note that the EPI signals must use 8-mA drive
when interfacing to SDRAM, see page 429. Any unused EPI controller signals can be used as GPIOs
or another alternate function.
Table 9-3. EPI SDRAM Signal Connections
EPI Signal
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20-EPI0S27
EPI0S28
EPI0S29
SDRAM Signal^a
A0
D0
A1
D1
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7
A8
D8
A9
D9
A10
D10
A11
D11
A12^b
D12
BA0
D13
BA1
D14
D15
DQML
DQMH
CASn
RASn
not used
WEn
CSn
January 22, 2012
465
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