LM3S5D91 Datasheet, PDF (839/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Stellaris^® LM3S5D91 Microcontroller
16.3.2.5
DMA Support
The µDMA can be used to more efficiently stream data to and from the I²S bus. The I²S transmit
and receive modules have separate µDMA channels. The FIFO Interrupt Mask bit (FFM) in the
I2SRXISM register must be set for the request signaling to propagate to the µDMA module. See
“Micro Direct Memory Access (μDMA)” on page 339 for channel configuration.
The I²S module uses the µDMA burst request signal, not the single request. Thus each time a µDMA
request is made, the µDMA controller transfers the number of items specified as the burst size for
the µDMA channel. Therefore, the µDMA channel burst size and the I²S FIFO service request limit
must be set to the same value (using the LIMIT field in the I2SRXLIMIT register).
16.4
Initialization and Configuration
The default setup for the I²S transmit and receive is to use external MCLK, external SCLK, Stereo,
I²S audio format, and 32-bit data samples. The following example shows how to configure a system
using the internal MCLK, internal SCLK, Compact Stereo, and Left-Justified audio format with 16-bit
data samples.
1. Enable the I²S peripheral clock by writing a value of 0x1000.0000 to the RCGC1 register in the
System Control module (see page 268).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 280). To find out which GPIO port to enable, refer to Table 23-5 on page 1206.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 425). To determine which GPIOs to configure, see Table
23-4 on page 1197.
4. Configure the PMCn fields in the GPIOPCTL register to assign the I²S signals to the appropriate
pins (see page 443 and Table 23-5 on page 1206).
5. Set up the MCLK sources for a 48-kHz sample rate. The input crystal is assumed to be 6 MHz
for this example (internal source).
■ Enable the PLL by clearing the PWRDWN bit in the RCC register in the System Control module
(see page 217).
■ Set the MCLK dividers and enable them by writing 0x0208.0208 to the I2SMCLKCFG register
in the System Control module (see page 232).
■ Enable the MCLK internal sources by writing 0x8208.8208 to the I2SMCLKCFG register in
the System Control module.
To allow an external MCLK to be used, set bits 4 and 5 of the I2SCFG register. Starting up the
PLL and enabling the MCLK sources is not required.
6. Set up the Serial Bit Clock SCLK source. By default, the SCLK is externally sourced.
■ Receiver: Masters the I2S0RXSCK by ORing 0x0040.0000 into the I2SRXCFG register.
■ Transmitter: Masters the I2S0TXSCK by ORing 0x0040.0000 into the I2STXCFG register.
7. Configure the Serial Encoder/Decoder (Left-Justified, Compact Stereo, 16-bit samples, 32-bit
system data size).
January 22, 2012
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