LM3S5D91 Datasheet, PDF (926/1340 Pages) Texas Instruments – Stellaris® LM3S5D91 Microcontroller

Universal Serial Bus (USB) Controller
registers for a given endpoint. As in Device mode, the FIFOs for endpoints should take into account
the maximum packet size for an endpoint.
■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the
maximum packet size if double buffering is used (described further in the following section).
■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice
the maximum packet size if double buffering is used.
■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint to communicate with a Device.
However, in most cases the USB controller should use the dedicated control endpoint to
communicate with a Device’s endpoint 0.
18.3.2.1
Endpoints
The endpoint registers are used to control the USB endpoint interfaces which communicate with
Device(s) that are connected. The endpoints consist of a dedicated control IN endpoint, a dedicated
control OUT endpoint, 15 configurable OUT endpoints, and 15 configurable IN endpoints.
The dedicated control interface can only be used for control transactions to endpoint 0 of Devices.
These control transactions are used during enumeration or other control functions that communicate
using endpoint 0 of Devices. This control endpoint shares the first 64 bytes of the USB controller’s
FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured
to communicate with control, bulk, interrupt, or isochronous Device endpoints.
These USB interfaces can be used to simultaneously schedule as many as 15 independent OUT
and 15 independent IN transactions to any endpoints on any Device. The IN and OUT controls are
paired in three sets of registers. However, they can be configured to communicate with different
types of endpoints and different endpoints on Devices. For example, the first pair of endpoint controls
can be split so that the OUT portion is communicating with a Device’s bulk OUT endpoint 1, while
the IN portion is communicating with a Device’s interrupt IN endpoint 2.
Before accessing any Device, whether for point-to-point communications or for communications via
a hub, the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB
Transmit Functional Address Endpoint n (USBTXFUNCADDRn) registers must be set for each
receive or transmit endpoint to record the address of the Device being accessed.
The USB controller also supports connections to Devices through a USB hub by providing a register
that specifies the hub address and port of each USB transfer. The FIFO address and size are
customizable and can be specified for each USB IN and OUT transfer. Customization includes
allowing one FIFO per transaction, sharing a FIFO across transactions, and allowing for
double-buffered FIFOs.
18.3.2.2
IN Transactions as a Host
IN transactions are handled in a similar manner to the way in which OUT transactions are handled
when the USB controller is in Device mode except that the transaction first must be initiated by
setting the REQPKT bit in the USBCSRL0 register, indicating to the transaction scheduler that there
is an active transaction on this endpoint. The transaction scheduler then sends an IN token to the
target Device. When the packet is received and placed in the receive FIFO, the RXRDY bit in the
USBCSRL0 register is set, and the appropriate receive endpoint interrupt is signaled to indicate
that a packet can now be unloaded from the FIFO.
When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn
register can be used to have RXRDY automatically cleared when a maximum-sized packet has been
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January 22, 2012
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