S71PL129JC0 Datasheet, PDF (82/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Symbol
Parameter
t_OH
t_PM
t_PC
t_AA
t_AOH
t_WC
t_WP
t_CW
t_BW
t_AW
t_AS
t_WR
t_CEH
t_WEH
t_ODW
t_OEW
t_DS
t_DH
t_CS
t_CH
t_DPD
t_CHC
t_CHP
Output Data Hold Time
Page Mode Time
Page Mode Cycle Time
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Set-up Time
Write Recovery Time
Chip Enable High Pulse Width
Write Enable High Pulse Width
WE# Low to Output High-Z
WE# High to Output Active
Data Set-up Time
Data Hold Time
CE2 Set-up Time
CE2 Hold Time
CE2 Pulse Width
CE2 Hold from CE1#
CE2 Hold from Power On
AC Test Conditions
Parameter
Output load
Input pulse level
Timing measurements
Reference level
t_R, t_F
Min Max
Unit
10
—
ns
70 10000 ns
30
—
ns
—
30
ns
10
—
ns
70 10000 ns
50
—
ns
70
—
ns
60
—
ns
60
—
ns
0
—
ns
0
—
ns
10
—
ns
6
—
ns
—
20
ns
0
ns
30
—
ns
0
—
ns
0
—
ns
300 —
µs
10
—
ms
0
—
ns
30
—
µs
Condition
30 pF + 1 TTL Gate
V_DD - 0.2 V, 0.2 V
V_DD x 0.5
V_DD x 0.5
5 ns
82
pSRAM Type 6
pSRAM_Type06_14_A1 Ocotober 16, 2004