S71PL129JC0 Datasheet, PDF (143/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance information
tWC
tWC
ADDRESS
ADDRESS VALID
ADDRESS VALID
CE1# _Low
tWR
tWR
WE#
LB#
UB#
DQ1-8
(Input)
DQ9-16
(Input)
tAS
tBS
tWHP
tBW
tBH
tDS
tDH
VALID DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
tBS
tAS
tBH
tBW
tDS
tDH
VALID DATA INPUT
Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
ADDRESS
CE1# _Low
tWC
ADDRESS VALID
tWC
ADDRESS VALID
WE#
LB#
DQ1-8
(Input)
UB#
DQ9-16
(Input)
tAS
tAS
tBW
tWR
tAS
tBWO _tDS
tDH
VALID
DATA INPUT
tBW
tWR
tBHP
tAS
tBHP
tDS
tDH
VALID
DATA INPUT
tBW
tWR
tDS
tDH
VALID
DATA INPUT
tBWO
tWR
tBW
tDS
tDH
VALID
DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 64. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
143