S71PL129JC0 Datasheet, PDF (122/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
16M pSRAM
Item
Average Operating
Current
Symbol
I_CC1
Async
I_CC2
Page
Standby Current (CMOS)
I_SB1 (Note 1)
Test Conditions
Min Typ Max Unit
Cycle time=1µs, 100% duty, I_IO=0mA,
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥V_CC-0.2V, V_IN≤0.2V or V_IN≥VCC-0.2V
— — 7 mA
Cycle time=Min, I_IO=0mA, 100% duty,
CS1#=V_IL, CS2=V_IH LB#=V_IL and/or UB#=V_IL, — — 30 mA
V_IN=V_IH or V_IL
Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty,
CS1#=V_IL, CS2=V_IH LB#=V_IL and/or UB#=V_IL,
V_IN-V_IH or V_IL
35 mA
Other inputs=0-VCC
1. CS1# ≥ V_CC - 0.2, CS2 ≥ V_CC - 0.2V (CS1#
controlled) or
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
— — 80 mA
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
32M pSRAM
Item
Average Operating
Current
Symbol
I_CC1
Async
I_CC2
Page
Standby Current (CMOS)
I_SB1 (Note 1)
Test Conditions
Min Typ Max Unit
Cycle time=1µs, 100% duty, I_IO=0mA,
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥V_CC-0.2V, V_IN≤0.2V or V_IN≥VCC-0.2V
— — 7 mA
Cycle time=Min, I_IO=0mA, 100% duty,
CS1#=V_IL, CS2=V_IH LB#=V_IL and/or UB#=V_IL, — — 35 mA
V_IN=V_IH or V_IL
Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty,
CS1#=V_IL, CS2=V_IH LB#=V_IL and/or UB#=V_IL,
V_IN-V_IH or V_IL
40 mA
Other inputs=0-VCC
1. CS1# ≥ V_CC - 0.2, CS2 ≥ V_CC - 0.2V (CS1#
controlled) or
— — 100 mA
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
122
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004